Field of the Invention
The present invention relates to a method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels, whereby the I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. Likewise, the invention relates to a computer program product with computer-implemented instructions, the product which after loading and execution in a suitable data processing device performs the steps of the above method, and a digital storage medium with electronically readable control signals, which can work together with a programmable data processing device, so that the above method is carried out in the data processing device. Further, the invention relates to a method for operating such a hardware component and a hardware component for executing the method.
Description of the Background Art
The real-time simulation of complex, dynamic models has high requirements because of the narrow time constraints even in modern computation nodes. For example, such models are used in automotive hardware-in-the-loop simulations (HIL), where fast control loops must be closed. This is the case, for instance, in the simulation of in-cylinder pressure sensors, which play an increasingly greater role in consumption or exhaust gas reduction. However, short cycle times and low latencies are indispensable also in controlled systems which have high dynamics, such as, for example, in electric motors. These can no longer be implemented practically with CPU-based simulations.
Field programmable gate arrays (FPGAs) can support hardware components during real-time simulation in that they take over the calculation of the dynamic parts of a model. Tough real-time requirements can also be easily met by the high flexibility and possibility of parallel processing of signals with the use of FPGAs. The FPGAs can be used in general as hardware accelerators for CPUs.
The described hardware components are used in two operating modes in the conventional art. In a first operating mode, a fixed functionality is loaded in the FPGA, as a result of which the FPGA is configured. I/O channels with a set functional scope are provided at the communications interface via this fixed functionality, so that the I/O channels can be used in an application in the processor. A user works in this first operating mode solely with a model-based generated processor application, e.g., with an RTI blockset. The application runs completely on the processor and accesses the I/O via the fixed FPGA functionality.
In a second operating mode, FPGA code generated model-based by the user is loaded into the FPGA, the code which uses the I/O channels in the FPGA. This refers, for example, to a control model in the FPGA or preprocessing of the I/O channels in the FPGA. The processor does not access the I/O channels in this operating mode. In this operating mode, the user works with a model-based generated FPGA application, e.g., with the RTI FPGA programming blockset. In addition, a processor application, which can communicate with the FPGA application, can be executed in the processor. However, the processor application cannot use the I/O channels with a set functional scope and a defined interface.